A Symmetric and Multilayer Reconfigurable Architecture for Hash Algorithm

As an essential protection mechanism of information security, hash algorithms are extensively used in various security mechanisms. The diverse application scenarios make the implementation more challenging regarding flexibility, performance, and resources. Since existing studies have such issues as wasted resources few supported when implementing algorithms, we proposed a new reconfigurable hardware architecture for common this paper. First, characteristics symmetry SM3 (Shang Mi 3) SHA2 (Secure Hash Algorithm 2) to design that also supports MD5 (Message Digest 5) SHA1 1) on both sides. Then split into two layers eliminated resource wastes introduced by different word widths through exploiting greater parallelism. Last, further divided four operators designed array. experimental results showed our can support types successfully, 32-bit 64-bit without wasting Compared with designs, has throughput rate improvement about 56.87–226% per up 5.5 times. Furthermore, utilization rose 80% or above executing algorithms.